1. Field of the Invention
This invention relates to, for example, a NOR type nonvolatile semiconductor memory device which stores multivalue data.
2. Description of the Related Art
For example, various types of nonvolatile semiconductor memory devices (which are hereinafter referred to as flash memories) which are configured by EEROM cells and in which data can be electrically and simultaneously erased are developed. The flash memories are roughly divided into NAND type memories and NOR type memories. In the flash memory of either type, it is required to precisely and rapidly control the threshold voltage set for the memory cell at the data write time or erase time. Conventionally, in the NAND type flash memory, a method to increase the write voltage in stages in order to precisely and rapidly set the threshold voltage is developed (for example, Jpn. Pat. Appln. KOKAI Publication No. H11-39887).
Recently, the technique for storing multivalue data of two bits (four valued) or more bits in one memory cell is developed with an increase in the memory capacity. When multivalue data of, for example, “00”, “01”, “10”, “11” is stored in one memory cell, it is required to more precisely control the threshold voltage of the memory cell in comparison with a case wherein binary data of only “0”, “1” is stored. However, in order to precisely adjust the threshold voltage, it is necessary to repeatedly perform the write and verify operations and a long time is required for adjustment in the conventional method for increasing the write voltage in stages. Therefore, since it is contrary to the requirement of enhancing the write operation speed, it becomes important to optimize the write sequence when multivalue data is stored. As a result, it is required to develop a nonvolatile semiconductor memory device which can optimize the multivalue data write sequence.